A flash memory device is a representative non-volatile semiconductor memory device, and includes memory blocks. Each of the memory blocks includes memory cells coupled to word lines, and respective memory cells include a tunnel insulation layer, a floating gate, an inter-poly dielectric and a control gate.
A program loop operation including a program operation and a program verification operation is performed based on an increment step pulse programming ISPP method, to store data in the memory cell. An erase loop operation including an erase operation and an erase verification operation is performed through an increment step pulse erasing ISPE method, to erase data.
To reduce a size of a chip, the size of the memory cell is decreased and a space between the memory cells is narrowed. In the event that high program voltage is supplied to control gates of the memory cells when the program operation is performed, electrons injected into the floating gate are discharged to the control gate through the inter-poly dielectric.